boxscore/security
CVE · referencelatest edition

Reference page — cumulative record through Monday, October 19, 2026 UTC. Reference pages update as the archive grows; only dated daily editions are immutable pages of record.

CVE-2020-24512

n/a Intel(R) Processors — Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure vi…
  AV  AC  PR  UI  S  C  I  A   CVSS    EPSS   %ile   KEV
   L   L   L   N  U  L  N  N    3.3   .0038   30.8     —
AFFECTED
  Product              Versions          Fixed
  Intel(R) Processors  See references –  —
TIMELINE
  Aug 19  Reserved by intel
  Jun 9   Published (CNA: intel)
  Oct 8   ENRICHED — CVE-2020-24512 (Intel(R) Processors). Received CVSS 3.3 and CPE data from NVD.
CWE-203 · CNA: intel · CVSS v3.1 · 5 references · NVD status: Modified

Description

Observable timing discrepancy in some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.

Lifecycle

Complete event history — 3 events, chronological
DateEventDetail
August 19, 2020ReservedReserved by intel
June 9, 2021PublishedPublished (CNA: intel)
October 8, 2026ENRICHEDENRICHED — CVE-2020-24512 (Intel(R) Processors). Received CVSS 3.3 and CPE data from NVD.

Affected

Affected products and packages — 1 row
VendorProduct / PackageEcosystemVersion introducedFixed
n/aIntel(R) Processors—See references—

Weaknesses

CWE-203

References (5)

Related

Authoritative record: CVE-2020-24512 at cve.org

Weaknesses: CWE-203

About this page

This is a reference page, not a dated page of record. It assembles the complete lifecycle of CVE-2020-24512 from the CVE Program record, NVD enrichment, the CISA KEV catalog, EPSS, and OSV advisories. The box score's numbers (CVSS, EPSS, KEV status) are current as of Monday, October 19, 2026 UTC and are re-derived as the archive grows; only dated daily editions are immutable pages of record. The authoritative source for this identifier is cve.org.